(1) Field of the Invention
The invention generally relates to the fabrication of semiconductor devices and, more particularly, to a method of forming an NMOS device for electrostatic discharge (ESD) protection in the fabrication of integrated circuits.
(2) Description of Prior Art
Integrated circuits (ICs) are susceptible to damage from a phenomenon called electrostatic discharge (ESD). ESD occurs during transportation and handling of the device when large static charges collect on their external pins. If not properly controlled, ESD will irreparably damage the IC as power dissipated during the discharge yields large temperature gradients within the device structure.
One solution to the problem of ESD is to connect a silicon controlled rectifier (SCR) on the IC near to the external pin bonding pad. When the voltage on the pad reaches a level beyond that of normal operation due to static charge, the SCR turns on, thereby providing a low resistance path for discharge. This protects the device by shunting this current away from the circuitry used in normal operation. Several approaches using SCRs exist. U.S. Pat. No. 5,369,041 to Duvvury teaches a method of building an SCR within a MOS process for the purpose of ESD protection. U.S. Pat. No. 5,728,612 to Wei et al. teaches a method of improving the performance of an SCR used for ESD protection. The resistance when the device is turn on is lowered by increasing the volume of contacts in the SCR by making the contact deeper in the IC. This improves the SCR performance without the need for increasing the size of the SCR. U.S. Pat. No. 5,843,813 to Wei et al. teaches another method of improving the performance of the ESD protection of an SCR that also reduces device switching noise. This device also uses deeper contacts to lower the resistance of the SCR when it is conducting.
A second method of ESD protection uses a grounded gate NMOS (GGNMOS) device to provide the low resistance discharge path. This is the protection method of the present invention. Refer now to FIG. 1 showing in cross section a typical GGNMOS device. It is to be understood that no portion of FIG. 1 is admitted to be prior art as to the present invention. Rather, this highly simplified diagram is provided in an effort to provide an improved understanding of the problems which are overcome by the present invention. A p-type well or substrate 10 is provided. A gate oxide 28 overlies the p-type well or substrate 10. A polysilicon gate electrode 30 overlies the gate oxide 28. N+ drain and source regions (14 and 22) are provided. A drain electrode 18 makes electrical connection to the drain 14, while a source electrode 26 makes electrical connection to the source 22. The source electrode 26 is connected to the gate electrode 30, both of which are connected to ground (as shown in FIG. 1) or to the most negative voltage potential used by the IC. For this description of the device operation, we will ground the source electrode 26 and gate electrode 30. While not shown, the p-type well or substrate 10 is also grounded. In order to provide a better electrical contact in active NMOS devices used on the IC, salicidation is performed on the upper surface of the n+ drain 14 and source 22 as shown in FIG. 1. Unfortunately, the salicidation reduces the ESD protection performance of a GGNMOS device due to discharge current localization. U.S. Pat. No. 6,100,125 to Hulfactor et al. teaches an ESD protection method using a GGNMOS device where drain contacts in the device are modified to reduce their conductivity. This is achieved by altering the lightly doped drain (LDD) region and by using a mask that prevents salicidation of the drain region.
Breakdown mechanisms provide the ESD protection in a GGNMOS device. Still referring to FIG. 1, those mechanisms will now be described. If the voltage on the drain electrode 18 is raised slightly above ground potential, the diode formed by p-type well 10 and drain region 14 will be reverse-biased and a depletion region will be formed between the two. A second depletion region exists between the source region 22 and the region of the p-type substrate or well 10 under the gate 30. This barrier holds the electrons in the source region 22. Any current that flows is due to leakage current in the reverse-biased drain/p-well junction.
If the drain electrode 18 voltage is increased, the depletion region between the p-type substrate or well 10 and drain region 14 will widen, moving it closer to the source region 22. When the voltage on the drain electrode 18 causes the drain depletion region to touch the source depletion region, the connection between the two depletion regions will have a low resistance. The result will be a very high current. This phenomenon is called xe2x80x9cpunch throughxe2x80x9d and the resulting current is called xe2x80x9cpunch through currentxe2x80x9d. The characteristic curves with the punch through phenomenon for a typical NMOS FET are shown in FIG. 2. A second phenomenon known as drain diode breakdown is shown in FIG. 2. Prior to drain diode breakdown, the current of a real reverse-biased drain junction does not saturate. This is due to the generation of electron-hole pairs when the diode is reversed biased; a fact often neglected in the ideal diode equation. Soft breakdown is the phenomenon where conduction results from excessive generation of electron-hole pairs. If the electric field reaches a critical level where hard breakdown occurs, a small increase in drain voltage will cause a very large increase in current.
FIG. 3 shows a plot of IDS vs. VDS for different source to drain well spacings. As the spacing is decreased, the leakage IDS increases. This occurs because the two depletion regions described above are moved closer to each other, resulting in significant field penetration from the drain to the source. The potential barrier at the source is lowered, resulting in increased injection of electrons by the source, giving rise to increased IDS. This is called drain induced barrier lowering (DIBL). Further increase of VDS will cause the depletion regions to touch resulting in punch through.
In some cases, a different phenomenon called xe2x80x9csnapbackxe2x80x9d occurs prior to reaching punch voltage. The present invention uses snapback to provide ESD protection. This phenomenon will be discussed in the description of the present invention.
A principal object of the present invention is to provide a semiconductor device that provides electrostatic discharge (ESD) protection.
Another object of the present invention is to provide a semiconductor device that provides electrostatic discharge (ESD) protection without requiring additional processing steps.
Another object of the present invention is to provide a semiconductor device that provides electrostatic discharge (ESD) protection that does not require the salicidation blocking step.
Another object of the present invention is to provide a semiconductor device that provides electrostatic discharge (ESD) protection that does not require an additional implantation to improve ESD characteristics.
A still further object of the present invention is to provide a semiconductor device that provides electrostatic discharge (ESD) protection having a trigger point away from the semiconductor surface.
These objects are achieved using a process where n-wells are added below the source and drain regions in a GGNMOS device. The n-well and p-well doping profiles are tailored such that the peaks of the well concentrations occur away from the silicon surface. This reduces the depletion barrier between the p-well and n-well source. In addition, the increased electric field between the reverse biased n-well drain and p-well will result in higher electron-hole generation current. This injects more holes into the p-well producing a potential that will forward bias the p-well/n-well source junction. The result is effectively a bipolar NPN transistor that is conducting. Low resistance between the drain and source quickly removes any electrostatic charge. The conduction occurs away from the silicon surface where power may be effectively dissipated.